x86 Opcode SYSENTER

Opcode SYSENTER

CPU: Intel Pentium II
Type of Instruction: System

Instruction: SYSENTER

Description:

if CR.0.PE == 0 then #GP(0);
if SYSENTER_CS_MSR == 0 then #GP(0);

EFLAGS.VM <- 0;
EFLAGS.IF <- 0;

CS.SEL <- SYSENTER_CS_MSR;
CPL <- 0;
CS.BASE <- 0;
CS.LIMIT <- 0xffff;
CS.ATTR.G <- 1;
CS.ATTR.S <- 1;
CS.ATTR.TYPE <- 1011b;
CS.ATTR.D <- 1;
CS.ATTR.DPL <- 0;
CS.RPL <- 0;
CS.ATTR.P <- 1;

SS.SEL <- CS.SEL+8;
SS.BASE <- 0;
SS.LIMIT <- 0xffff;
SS.ATTR.G <- 1;
SS.ATTR.S <- 1;
SS.ATTR.TYPE <- 0011b;
SS.ATTR.D <- 1;
SS.ATTR.DPL <- 0;
SS.RPL <- 0;
SS.ATTR.P <- 1;

ESP <- SYSENTER_ESP_MSR;
EIP <- SYSENTER_EIP_MSR;

Note: How to check if this instruction present:
CPUID.SEP bit must be set.
AND
CPUID.FAMILY == 6 AND (CPUID.MODEL >=3) AND (CPUID.STEP >= 3)

Note: See MSR List for more Info. (MSRs 174h,175h,176h)

Note: Passing control to fixed entry point for faster OS calls.

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COP & Times:

SYSENTER 0FH 34H
P6: n/a