Opcode SVDC
CPU: Cyrix Cx486S/S2/D/D2/DX/DX2/DX4
IBM BL486DX/DX2
TI 486SLC/DLC/e
TI 486SXL/SXL2/SXLC
TI Potomac
Type of Instruction: System
Instruction: SVDC dest,sreg
Description:
dest <- sreg [selector,shadow_descriptor]
; dest is register and descriptor structure (see below)
Format or Register and Descriptor Structure:
+00 Limit (15-0)
+02 Base (15-0)
+04 Base (23-16)
+05 AR byte
+06 AR2/Limit (19-16)
+07 Base (31-24)
+08 Selector
Length of structure is 0Ah
Flags Affected: None
CPU mode: (1) and (2) and (3) and [(4A) or (4B)]
1) CPL=0
2) CCR1.bit1=1 ; SMI enable
3) SMAR size > 0
4A) in SMM
4B) CCR1.bit2=1 ; SMAC is on
++++++++++++++++
Physical Form: SVDC mem80,sreg
COP (Code of Operation) : 0FH 78H [mm sreg3 mmm]
Clocks IBM BL486DX: 18
TI 486SXL : 22
Note: sreg3 is: 000 ES
001 CS
010 SS
011 DS
100 FS
101 GS
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