x86 Opcode RSM

Opcode RSM

CPU: I486 SL Enhanced+,i486SL,i386CX,i386EX
Type of Instruction: System

Instruction: RSM

Description:

Restore execution state from SMRAM and
return to previous CPU mode

CPU mode: SMM only
( INT 6 - Undefined Opcode in all other mode )

Flags Affected: All

Note: CPU state restored from dump created entrance to SMM.
The CPU leave SMM and return to previous mode.
If CPU detect any invalid state it enters shutdown.
This invalid states is:
* The value stored in State Dump Base field is not 32K aligned
address
* Any Reserved bit of CR4 is set to 1 (Pentium only)
* Any illegal Combination of CR0:
** (PG=1 and PE=0)
** (NW=1 and CD=0)

Format of Execution State in SMRAM:
Offset Register
7FFCh CR0
7FF8h CR3
7FF4h EFLAGS
7FF0h EIP
7FECh EDI
7FE8h ESI
7FE4h EBP
7FE0h ESP
7FDCh EBX
7FD8h EDX
7FD4h ECX
7FD0h EAX
7FCCh DR7
7FC4h TR, upper 2 bytes reserved
7FC0h LDTR, upper 2 bytes reserved
7FBCh GS, upper 2 bytes reserved
7FB8h FS, upper 2 bytes reserved
7FB4h DS, upper 2 bytes reserved
7FB0h SS, upper 2 bytes reserved
7FACh CS, upper 2 bytes reserved
7FA8h ES, upper 2 bytes reserved
7F98h Reserved
7F94h IDT base (4 bytes)
7F8Ch Reserved
7F88h GDT base (4 bytes)
7F04h Reserved
7F02h Auto HALT Restart Slot (2 bytes)
Bits 15..2 are reserved
Bit 1 Bit 0 Description
0 0 Resume to next instruction in interrupted
program
0 1 Unpredictable
1 0 Return to next instruction after HALT
1 1 Return to HALT state
7F00h I/O Restart Slot (2 bytes)
When RSM execution if I/O restart slot = 0FFh then
EIP modified to instruction immediate preceding the
SMI# request i.e. CPU automatically reexecute I/O
instruction which be trapped by SMI.
7EFCh SMM Revision Identificator (4 bytes)
Bits Description
31..18 Reserved
17 If=1 Processor support SMBASE relocation
else not support
16 If =1 Processor support I/O Instruction Restart
15..0 SMM Revision Identificator
P5,486s = 0000h
P54C when I/O Restarts enable = 0002h
7EF8h SMBASE Slot (4 bytes)
SMBASE is 32KB aligned 32bit dword which contained a base
address for SMRAM.
Default value is 30000h
Starting Address for for jump in SMM is:
SMBASE+8000h
Starting address for State Save area is
SMBASE+[8000h+7FFFh]
7E00h Reserved

Note: In fields marked Reserved saved and restores next registers:
CR1,CR2,CR3, hidden descriptors for CS,DS,ES,FS,SS,GS.
Never saved registers: DR5-DR0,TR7-TR3,all FPU registers.
More Information Not available Yet.

Physical Form: RSM
COP (Code of Operation) : 0FH AAH
Clocks: i386CX : 338
i486 SL Enhanced : ???
IntelDX4 : 452 ; SMBASE relocation
: 456 ; AutoHALT restart
: 465 ; I/O Trap restart
Pentium : 83