x86 Opcode RDTSC

Opcode RDTSC

CPU: Pentium (tm), Pentium Pro, AMD Am5k86
Type of Instruction: System/User

Instruction: RDTSC

Description:

IF (CR4.TSD=0) or ((CR4.TSD=1) and (CPL=0)) THEN
{
EDX:EAX <- TSC;
}
ELSE
{
General Protection Fault INT 0DH (0)
}
END

Note: TSC is one of MSR and after global hardware reset (not SRESET , but
RESET ) it clear to 0000000000000000H.
TSC is MSR index 10h. TSC may set using WRMSR instruction.
TSC incremented every CPU core clock cycle.

Flags Affected: None

CPU mode: RM,PM0,SMM
; PM,VM if enable

Physical Form: RDTSC
COP (Code of Operation): 0FH 31H
Clocks: Pentium : n/a [20-24]