Opcode PUNPCKLBW
CPU: all which supported IA MMX:
Pentium (P55C only), Pentium (tm) Pro (P6) future models
Type of Instruction: User
Instruction: PUNPCKLBW dest,src
Description:
dest[63..56] <- src[31..24]
dest[55..48] <- dest[31..24]
dest[47..40] <- src[23..16]
dest[39..32] <- dest[23..16]
dest[31..24] <- src[15..8]
dest[23..16] <- dest[15..8]
dest[15..8] <- src[7..0]
dest[7..0] <- dest[7..0]
Note: This instruction unpack and interleave the low-order data elements
of the destination and source operands into the destination operand.
The high-order data elements are ignored.
When the source data comes from 64-bit registers, the upper 32 bits
are ignored.
When unpacking from a memory operand, only 32 bits are accessed. The
instruction uses all 32 bits.
If the source operand is all zeros, the result is a zero extension of
the low-order elements of the destination operand. When using
PUNPCKLBW instruction the bytes are zero extended, or unpacked into
unsigned words.
Flags affected: None
Exceptions:
RM PM VM SMM Description
#GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS
#SS(0) If illegal memory operand's EA in SS
#PF(fcode) If page fault
#AC #AC If unaligned memory reference then alignment
check enabled and in ring 3.
#UD #UD #UD #UD If CR0.EM = 1
#NM #NM #NM #NM If CR0.TS = 1
#MF #MF #MF #MF If pending FPU Exception
#13 #13 If any part of the the operand lies outside of
the EA space from 0 to FFFFH
++++++++++++++++++++++++++++++++++++++
COP & Times:
PUNPCKLBW mm,mm/m32 0FH 60H PostByte
P55C: n/a
future P6: n/a
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