CPU: all which supported IA MMX:
Pentium (P55C only), Pentium (tm) Pro (P6) future models
Type of Instruction: User

Instruction: PSUBSB dest,src


dest[7..0] <- SaturateToSignedByte(dest[7..0] - src[7..0])
dest[15..8] <- SaturateToSignedByte(dest[15..8] - src[15..8])
dest[23..16] <- SaturateToSignedByte(dest[23..16] - src[23..16])
dest[31..24] <- SaturateToSignedByte(dest[31..24] - src[31..24])
dest[39..32] <- SaturateToSignedByte(dest[39..32] - src[39..32])
dest[47..40] <- SaturateToSignedByte(dest[47..40] - src[47..40])
dest[55..48] <- SaturateToSignedByte(dest[55..48] - src[55..48])
dest[63..56] <- SaturateToSignedByte(dest[63..56] - src[63..56])

Note: This instruction subtract signed packed byte in MMXregister/memory
from signed packed byte in MMX register and saturate.
If the result is larger or smaller than the range of a signed byte,
the value is saturated; in the case of an overflow - to 7FH, and the
case of an underflow - to 80H

Flags affected: None


RM PM VM SMM Description
#GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS
#SS(0) If illegal memory operand's EA in SS
#PF(fcode) If page fault
#AC #AC If unaligned memory reference then alignment
check enabled and in ring 3.
#UD #UD #UD #UD If CR0.EM = 1
#NM #NM #NM #NM If CR0.TS = 1
#MF #MF #MF #MF If pending FPU Exception
#13 #13 If any part of the the operand lies outside of
the EA space from 0 to FFFFH
COP & Times:

PSUBSB mm,mm/m64 0FH E8H PostByte

P55C: n/a
future P6: n/a

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