Opcode PSLLW


CPU: all which supported IA MMX:
Pentium (P55C only), Pentium (tm) Pro (P6) future models
Type of Instruction: User

Instruction: PSLLW dest,src

Description:

temp <- src
dest[15..0] <- dest[15..0] << temp
dest[31..16] <- dest[31..16] << temp
dest[47..32] <- dest[47..32] << temp
dest[63..48] <- dest[63..48] << temp

Note: Shift words in MMX register left by Imm8 or amount specified in MMX
register/memory, while shifting in zeros.

Flags affected: None

Exceptions:

RM PM VM SMM Description
#GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS
#SS(0) If illegal memory operand's EA in SS
#PF(fcode) If page fault
#AC #AC If unaligned memory reference then alignment
check enabled and in ring 3.
#UD #UD #UD #UD If CR0.EM = 1
#NM #NM #NM #NM If CR0.TS = 1
#MF #MF #MF #MF If pending FPU Exception
#13 #13 If any part of the the operand lies outside of
the EA space from 0 to FFFFH
++++++++++++++++++++++++++++++++++++++
COP & Times:

PSLLW mm,mm/m64 0FH F1H PostByte
PSLLW mm,Imm8 0FH 71H/6 PostByte ImmData

P55C: n/a
future P6: n/a


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