x86 Opcode PCMPEQB

Opcode PCMPEQB

CPU: all which supported IA MMX:
Pentium (P55C only), Pentium (tm) Pro (P6) future models
Type of Instruction: User

Instruction: PCMPEQB dest,src

Description:

IF dest[7..0] = src[7..0]
THEN
dest[7..0] <- FFH
ELSE
dest[7..0] <- 00H
IF dest[15..8] = src[15..8]
THEN
dest[15..8] <- FFH
ELSE
dest[15..8] <- 00H
IF dest[23..16] = src[23..16]
THEN
dest[23..16] <- FFH
ELSE
dest[23..16] <- 00H
IF dest[31..24] = src[31..24]
THEN
dest[31..24] <- FFH
ELSE
dest[31..24] <- 00H
IF dest[39..32] = src[39..32]
THEN
dest[39..32] <- FFH
ELSE
dest[39..32] <- 00H
IF dest[47..40] = src[47..40]
THEN
dest[47..40] <- FFH
ELSE
dest[47..40] <- 00H
IF dest[55..48] = src[55..48]
THEN
dest[55..48] <- FFH
ELSE
dest[55..48] <- 00H
IF dest[63..56] = src[63..56]
THEN
dest[63..56] <- FFH
ELSE
dest[63..56] <- 00H

Note: Compare packed byte in MMXregister/memory with packed byte in MMX
register for equality.

Flags affected: None

Exceptions:

RM PM VM SMM Description
#GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS
#SS(0) If illegal memory operand's EA in SS
#PF(fcode) If page fault
#AC #AC If unaligned memory reference then alignment
check enabled and in ring 3.
#UD #UD #UD #UD If CR0.EM = 1
#NM #NM #NM #NM If CR0.TS = 1
#MF #MF #MF #MF If pending FPU Exception
#13 #13 If any part of the the operand lies outside of
the EA space from 0 to FFFFH
++++++++++++++++++++++++++++++++++++++
COP & Times:

PCMPEQB mm,mm/m64 0FH 74H PostByte

P55C: n/a
future P6: n/a