Opcode MOVQ
CPU: all which supported IA MMX:
Pentium (P55C only), Pentium (tm) Pro (P6) future models
Type of Instruction: User
Instruction: MOVQ dest,src
Description:
dest <- src
Note: This instruction moved QWORDs to/from MMX registers
Of course, IA support Big-endian QWORDS.
Flags affected: None
Exceptions:
RM PM VM SMM Description
#GP(0) If result in Non-Writable segment
#GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS
#SS(0) If illegal memory operand's EA in SS
#PF(fcode) If page fault
#AC #AC If unaligned memory reference then alignment
check enabled and in ring 3.
#UD #UD #UD #UD If CR0.EM = 1
#NM #NM #NM #NM If CR0.TS = 1
#MF #MF #MF #MF If pending FPU Exception
++++++++++++++++++++++++++++++++++++++
COP & Times:
MOVQ mm,mm/m64 0FH 6FH PostByte
MOVQ mm/m64,mm 0Fh 7Fh PostByte
Note: In PostByte instead IU registers used MMX registers,
0Fh 6Fh C0h means MOVQ MM0,MM0
mm,r/m32 r/m32,mm
P55C: n/a (~1) (~1)
future P6: n/a (~1) (~1)
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