Opcode CPUID
CPU: Intel 486DX/SX/DX2 SL Enhanced and all later
Intel processors include ( IntelDX4, IntelSX2,
Pentium etc.), UMC microprocessors: U5S,U5SD,U5S-VL.
Cyrix M1, AMD K5, Intel P6, and AMD Ehnanced Am486 CPU,
such as A80486DX4-100SV8B.
Note: i.e. 1993+ years processors produced by Intel
Note: To know if your CPU support CPUID instruction
try to set ID flag ( bit 21 of EFLAGS ) to 1, and
if it sets this mean that CPUID support.(Soft).
Or If Your CPU is Intel Look for '&E' signature on
Top side of Chip.(Hard)
Type of Instruction: Operation
Instruction: CPUID
Description:
IF (EAX=0) THEN // All
{
EAX <- Maximum value of EAX to CALL CPUID instruction
1 for all processors (date 1 September 1994)
may be >1 in future microprocessors
;; EBX,EDX and ECX contain a OEM name string
;; for Intel this string is 'GenuineIntel'
EBX <- 756E6547H i.e. 'Genu'
EDX <- 49656E69H i.e. 'ineI'
ECX <- 6C65746EH i.e. 'ntel'
;; for UMC this string is 'UMC UMC UMC '
EBX <- 20434D55H i.e. 'UMC '
EDX <- 20434D55H i.e. 'UMC '
ECX <- 20434D55H i.e. 'UMC '
;; for Cyrix this string is 'CyrixInstead' (Cx6x86,Cx5x86 steps B+)
;; for AMD this string is 'AuthenticAMD' (K6,K5,486 Enhanced CPUs)
;; for last NexGen is 'NexGenDriven' (Nx5x86 latest models)
;; for Centaur Technology is 'CentaurHauls' (IDT)
;; for Rise Technology is 'RiseRiseRise'
}
ELSEIF (EAX=1) THEN // All
{
EAX[3:0] <- Stepping ID
EAX[7:4] <- Model
EAX[11:8] <- Family
; 3 - 386 family
; 4 - i486 family
; 5 - Pentium family
; 6 - Pentium Pro family
EAX[15:12] <- Reserved
; 0 - Original OEM processor
; 1 - OverDrive
; 2 - Dual Processor
Note: Pentium P54C have pin CPUTYPE which
define is this CPU First or Second e.t.c
in System.
So, if this chip set in "First" socket it
return for example 0425h, but THIS chip
return 2425h if we insert it in "Second"
socket.
Note: Refer to Appendix B for more information.
EAX[31:16] <- Reserved and set to 0s now
Note: This value in EAX[31:0] is upper 32-bit of 96-bit processor
serial number.
EDX <- Compability flags
;; below all info if bit flag =1
EDX[0] <- FPU: FPU on Chip
EDX[1] <- VME: Virtual Mode Extention present
EDX[2] <- DE: Debbuging Extentions
EDX[3] <- PSE: CPU support 4MB size pages
EDX[4] <- TSC: TSC present (See RDTSC command)
EDX[5] <- MSR: CPU have Pentium Compatible MSRs
EDX[6] <- PAE: Physical Address Extension (Intel)
EDX[6] <- PTE: Support PTE (Cyrix)
When set in PTE TLB will not be flushed
when CR3 is written.
EDX[7] <- MCE: Machine Check exception
EDX[8] <- CX8: Support CMPXCHG8B instruction
EDX[9] <- APIC: Local APIC on Chip (Intel)
PGE: Page Global Extension (K5)
EDX[10]<- reserved
EDX[11]<- SEP: Fast System Call feature (Pentium Pro)
EDX[12]<- MTRR: CPU support Memory Type Range Register (MTRR)
EDX[13]<- PGE: Page Global Feature support
EDX[14]<- MCA: Machine Check Architecture
EDX[15]<- CMOV: CPU support CMOV instruction
EDX[16]<- PAT: Page Attribute Table
EDX[17]<- PSE36: CPU support 4MB Pages for access memory higher
that 2GB.
EDX[18]<- SN: CPU Support Processor Serial Number
EDX[22..19] <- Reserved
EDX[23] <- MMX: CPU support IA MMX
EDX[24] <- FXSR: CPU Support Fast Save/Restore (IA MMX-2)
EDX[25] <- SIMD: Streaming SIMD Extension (IA MMX-2)
EDX[31:26] <- Reserved and set to 0s now
}
ELSEIF (EAX=2)
{
AL = 1 (Pentium Pro, Pentium II)
remainder of EAX and EBX,ECX,EDX contain bytes which
described cache architecture on this chip.
Description of this bytes is:
Value Description
00h None
01h Instruction TLB, 4K page, 4way, 64 entry
02h Instruction TLB, 4M page, 4way, 4 entry
03h Data TLB, 4K page, 4way, 64 entry
04h Data TLB, 4M page, 4way, 8 entry
06h Instruction Cache, 8K, 4 way, 32 byte per line
08h Instruction Cache, 16K, 4 way, 32 byte per line
0Ah Data cache, 8K, 2 way, 32 byte per line
0Ch Data cache, 16K, 4 way, 32 byte per line
40h No L2 cache
41h Unifed L2 cache, 32 byte per line, 4 way, 128KB
42h Unifed L2 cache, 32 byte per line, 4 way, 256KB
43h Unifed L2 cache, 32 byte per line, 4 way, 512KB
44h Unifed L2 cache, 32 byte per line, 4 way, 1MB
45h Unifed L2 cache, 32 byte per line, 4 way, 2MB
(Cyrix MediaGX MMX Enhanced)
70h TLB 32-bit entry, 4 way, 4K cache
80h L1 cache 4-way associative, 16byte/line
}
ELSEIF (EAX = 3) // Pentium III
{
EDX:ECX <- Lower 64-bit of 96-bit processor serial number.
}
ELSEIF (EAX = 80000000h) // (K5 not SSA/5),K6, Cyrix GXm
{
EBX,ECX,EDX <- Undefined
EAX <- Largest Extended function value recognized by CPUID.
(Note: Extended CPUID functions started with 80000000h)
(Example: For AMD 5k86 (K5) = 80000005h )
}
ELSEIF (EAX = 80000001h) // K5,K6,Cyrix GXm,IDT Winchip 2
{
EAX <- AMD Processor Signature
0000051Xh - for AMD 5k86 (K5 not SSA/5)
0000066Xh - for AMD 6k86 (K6)
EBX,ECX <- Undefined
EDX <- Extended Feature Flags
EDX[0] <- FPU: FPU on Chip
EDX[1] <- VME: Virtual Mode Extention present
EDX[2] <- DE: Debbuging Extentions
EDX[3] <- PSE: CPU support 4MB size pages
EDX[4] <- TSC: TSC present (See RDTSC command)
EDX[5] <- MSR: CPU have K5 Compatible MSRs
or Cyrix Compatible MSRs
EDX[6] <- PAE: Page Address Extensions
EDX[7] <- MCE: Machine Check exception
EDX[8] <- CX8: Support CMPXCHG8B instruction
EDX[9] <- APIC: CPU have local APIC (must be enabled)
EDX[10] <- Reserved
EDX[11] <- SYSCALL and SYSRET Instructions (!)
EDX[12]<- MTRR: Memory Type Range Registers
EDX[13]<- Global Paging Extensions (PTE-PGE)
EDX[14]<- MCA: Machine Check Architecture
EDX[15]<- CMOV: CPU support CMOV instruction (!)
EDX[16]<- FCMOV: CPU support FP. FCMOV (!)
EDX[17]<- PSE: Page Size Extention
EDX[21..18] <- Reserved
EDX[22] <- MMXE: CPU Support Extended MMX instructions
(AMD Athlon)
EDX[23] <- MMX: CPU support IA MMX
EDX[24] <- (Cyrix) Cyrix Extended MMX support
EDX[24] <- (AMD) FXSAVE/FXRSTOR instruction support
EDX[29..24] <- Reserved
EDX[30] <- CPU support Extended 3DNow! Instructions
EDX[31] <- AMD 3DNow! support
;Note: For AMD K5 = 000021BFh
For AMD K6 = 008005BFh
}
ELSEIF (EAX = 80000002h,80000003h,80000004h) // AMD K5,K6, Cyrix GXm
{ // IDT Winchip 2
EAX, EBX, ECX ,EDX = CPU Name
// Note: for AMD K5 (Don't forget x86 is BIG-Endian!!)
// CPUID(EAX) EAX EBX ECX EDX
// 80000002h 2D444D41 7428354B 5020296D 65636F72
// AMD- K5(r m) P roce
// 80000003h 726F7373 00000000 00000000 00000000
// ssor
// 80000004h 00000000 00000000 00000000 00000000
}
ELSEIF (EAX = 80000005h) // AMD K5,K6,Cyrix GXm
{ // L1 TLB and Cache information
EAX <- TLB Information (for 2M/4M pages):
see format of EBX.
EBX <- TLB Information (for 4K pages):
EBX[31..24] <- Data TLB: Associativity
(if Full assocuiativity = FFh)
see CPUID 80000006h for more datails
EBX[23..16] <- Data TLB: Number of Entryes
EBX[15..8] <- Instruction TLB: Associativity
(if Full assocuiativity = FFh)
EBX[7..0] <- Instruction TLB: Number of Entryes
ECX <- L1 Data Cache Information
ECX[31..24] <- Size in KB
ECX[23..16] <- Associativity (if full = FFh)
ECX[15..8] <- Lines per Tag
ECX[7..0] <- Line size in Bytes
EDX <- L1 Instruction Cache Information
ECX[31..24] <- Size in KB
ECX[23..16] <- Associativity (if full = FFh)
ECX[15..8] <- Lines per Tag
ECX[7..0] <- Line size in Bytes
// Note: after execution CPUID with EAX = 80000005h
// reg AMD K5 AMD K6
// EBX 04800000 02800140
// ECX 08040120 20020220
// EDX 10040120 20020220
}
ELSE THEN (EAX = 80000006h) // K6-III model-9, AMD Athlon
{ // L2 cache and TLB information
EAX = 2M/4M Pages and L2 TLB Info
bits description
31..28 Associativity (L2 Data TLB)
0000 L2 off
0001 Direct Mapped
0010 2-Way
0100 4-Way
0110 8-Way
1000 16-Way
1111 Full
27..16 Number of Entries (L2 Data TLB)
15..12 Associativity (L2 Instruction or Unifed TLB)
11..0 Number of entries (L2 Instruction or Unifed TLB)
EBX = 4K Pages and L2 TLB Info
bits description
31..28 Associativity (L2 Data TLB)
27..16 Number of Entries (L2 Data TLB)
15..12 Associativity (L2 Instruction or Unifed TLB)
11..0 Number of entries (L2 Instruction or Unifed TLB)
ECX = L2 Unifed Cache Info (K6-III: only this field)
bits description
31..16 Size (KB)
15..12 Associativity
11..8 Lines per tag
7..0 Line size (bytes)
EDX = reserved
}
ELSE THEN
{
EAX,EBX,ECX,EDX <- Undefined
}
END.
------------------------------------------------------
Notes: In Tables Below, you may see that Your CPU return other features
values, so in this tables, values writed on maximal. So possibly
some features exists on Your CPU, but not activated in time You
test, so CPUID return less functions that processor really can
support
------------------------------------------------------
Table of STANDART Features (CPUID/EAX=1) by Different Vendors
Media
(Cyrix) 6x86 6x86L GX 6x86MX MII GXm
EDX[0] <- FPU: + + + + + +
EDX[1] <- VME: - - - - - -
EDX[2] <- DE: - + - + + -
EDX[3] <- PSE: - - - - - -
EDX[4] <- TSC: - - - + + +
EDX[5] <- MSR: - - - + + +
EDX[6] <- PAE: - - - - -
EDX[6] <- PTE: ?
EDX[7] <- MCE: - - - - - -
EDX[8] <- CX8: - + - + + +
EDX[9] <- APIC: - - - - -
EDX[10]<- res - - - - - -
EDX[11]<- SEP: - - - - - -
EDX[12]<- MTRR: - - - - - -
EDX[13]<- PGE: - - - + + -
EDX[14]<- MCA: - - - - - -
EDX[15]<- CMOV: - - - + + +
EDX[16]<- PAT: - - - - - -
EDX[17]<- PSE36:- - - - - -
EDX[18]<- SN: - - - - - -
EDX[23]<- MMX: - - - + + +
EDX[24]<- FXSR: - - - - - -
EDX[25]<- SIMD: - - - - - -
IDT IDT AMD AMD AMD AMD AMD
(IDT/AMD) C6 C2 K5 K6 K6-2 K6-III Athlon
EDX[0] <- FPU: + + + + + + +
EDX[1] <- VME: - - + + + + +
EDX[2] <- DE: + + + + + + +
EDX[3] <- PSE: - - + + + + +
EDX[4] <- TSC: + + + + + + +
EDX[5] <- MSR: + + + + + + +
EDX[6] <- PAE: - - - - - - +
EDX[7] <- MCE: + + + + + + +
EDX[8] <- CX8: + + + + + + +
EDX[9] <- APIC: - - - - - x
EDX[9] <- GPE +
EDX[10]<- res - - - - - - -
EDX[11]<- SEP: - - - - - - +
EDX[12]<- MTRR: - - - - - - +
EDX[13]<- PGE: - - - - - - +
EDX[14]<- MCA: - - - - - - +
EDX[15]<- CMOV: - - - - - - +
EDX[16]<- PAT: - - - - - - +
EDX[17]<- PSE36:- - - - - - -
EDX[18]<- SN: - - - - - - -
EDX[23]<- MMX: + + - + + + +
EDX[24]<- FXSR: - - - - - - -
EDX[25]<- SIMD: - - - - - - -
Pentium Pentium Pentium Pentium
(Intel) Pentium w/MMX Pro II III Celeron
EDX[0] <- FPU: + + + + + +
EDX[1] <- VME: + + + + + +
EDX[2] <- DE: + + + + + +
EDX[3] <- PSE: + + + + + +
-------------------------------------------------------
EDX[4] <- TSC: + + + + + +
EDX[5] <- MSR: + + + + + +
EDX[6] <- PAE: - - + + + +
EDX[7] <- MCE: + + + + + +
-------------------------------------------------------
EDX[8] <- CX8: + + + + + +
EDX[9] <- APIC: (1) (1) (1) (1) (1) (1)
EDX[10]<- res - - - - ? -
EDX[11]<- SEP: - - + + + +
-------------------------------------------------------
EDX[12]<- MTRR: - - + + + +
EDX[13]<- PGE: - - + + + +
EDX[14]<- MCA: - - + + + +
EDX[15]<- CMOV: - - + + + +
-------------------------------------------------------
EDX[16]<- PAT: - - - (2) + +
EDX[17]<- PSE36:- - - (2) + +
EDX[18]<- SN: - - - - + -
EDX[23]<- MMX: - + - + + +
EDX[24]<- FXSR: - - - (2) + +
EDX[25]<- SIMD: - - - - + -
(1) = Intel produce chips with APIC and w/o APIC.
(2) = It start to support since "Deschutes" core
SL_enh SL_enh WB_Enh Intel Pentium UMC AMD
i486SX DX/DX2 i486DX2 DX4 OVDR U5S 5x86
EDX[0] <- FPU: - + + + + - +
EDX[1] <- VME: + + + + + - -
EDX[2] <- DE: - - - - + - -
EDX[3] <- PSE: - - + + + - -
-------------------------------------------------------
EDX[4] <- TSC: - - - - + - -
EDX[5] <- MSR: - - - - + - -
EDX[6] <- PAE: - - - - - - -
EDX[7] <- MCE: - - - - - - -
-------------------------------------------------------
EDX[8] <- CX8: - - - - + - -
EDX[9] <- APIC: - - - - - - -
no need to look higher flags, theys is 0s.
------------------------------------------------------
Table of EXTENDED Features (CPUID/EAX=80000001) by Different
Vendors
Cyrix IDT IDT AMD AMD AMD AMD
GXm C6 C2 K6 K6-2 K6-III Athlon
EDX[0] <- FPU: + + + + + + +
EDX[1] <- VME: - - - + + + +
EDX[2] <- DE: - + + + + + +
EDX[3] <- PSE: - - - + + + +
EDX[4] <- TSC: + + + + + + +
EDX[5] <- MSR: + + + + + + +
EDX[6] <- PAE: - - - - - - +
EDX[7] <- MCE: - + + + + + +
EDX[8] <- CX8: + + + + + + +
EDX[9] <- APIC: - - - - - - *
EDX[10]<- res - - - + - - -
EDX[11]<- SCL - - - - + + +
EDX[12]<- MTRR - - - - - - +
EDX[13]<- GPE - - - - + + +
EDX[14]<- MCE - - - - - - +
EDX[15]<- CMOV + - - - - - +
EDX[16]<- PAT ? - - - - - +
EDX[17]<- PSE36 - - - - - - -
EDX[22]<- AMMX - - - - - - +
EDX[23]<- MMX + + + + + + +
EDX[24]<- EMMX + - - - - - -
EDX[30]<- E3D! - - - - - - +
EDX[31]<- 3D! - - + - + + +
Refer to: Appendix B for more informations about CPU codes.
Note: On IDT C6 CPU we may set any Identification string and family/model/
stepping info. (See MSRs 108h,109h for More Details).
Here is 3 examples of Information we can may get from CPUID instruction:
1) UMC U5S
Note: All UMC Chips: U5S,U5SD, 3V chips never have FPU on-chip,
and never support VME
Maximum Available of CPUID info entrys:1
Vendor string is : "UMC UMC UMC "
Model Info :
Stepping ID is : 3
Model : 2
Family : 4
M field : 0
Compability Flags:
FPU on Chip :-
Virtual Mode Extensions present :-
CPU support I/O breakpoints :-
CPU support 4MB pages :-
Time Stamp Counter Presents :-
CPU have Pentium compatible MSRs :-
Machine Check Exception Presents :-
CMPXCHG8B instruction support :-
APIC on Chip :-
2) Intel 486
Note: All SL Enhanced 486: { i486SX,i486DX,i486DX2 marked '&E' on chip
surface }, IntelSX2,IntelDX4 support VME !!!!
But: Sxs never have FPU on chip.
Maximum Available of CPUID info entrys:1
Vendor string is : "GenuineIntel"
Model Info :
Stepping ID is : 0
Model : 8
Family : 4
M field : 0
Compability Flags:
FPU on Chip :+
Virtual Mode Extensions present :+
CPU support I/O breakpoints :-
CPU support 4MB pages :-
Time Stamp Counter Presents :-
CPU have Pentium compatible MSRs :-
Machine Check Exception Presents :-
CMPXCHG8B instruction support :-
APIC on Chip :-
3) Pentium
Note: P54C may say that build-in APIC not present if it
not supported by external hardware !!!!! (This data from
P54C in single processor configuration)
Maximum Available of CPUID info entrys:1
Vendor string is : "GenuineIntel"
Model Info :
Stepping ID is : 1
Model : 2
Family : 5
M field : 0
Compability Flags:
FPU on Chip :+
Virtual Mode Extensions present :+
CPU support I/O breakpoints :+
CPU support 4MB pages :+
Time Stamp Counter Presents :+
CPU have Pentium compatible MSRs :+
Machine Check Exception Presents :+
CMPXCHG8B instruction support :+
APIC on Chip :-
4) Pentium OverDrive
Note: P24T never have Machine Check Exception
Maximum Available of CPUID info entrys:1
Vendor string is : "GenuineIntel"
Model Info :
Stepping ID is : 1
Model : 3
Family : 5
M field : 1
Compability Flags:
FPU on Chip :+
Virtual Mode Extensions present :+
CPU support I/O breakpoints :+
CPU support 4MB pages :+
Time Stamp Counter Presents :+
CPU have Pentium compatible MSRs :+
Machine Check Exception Presents :-
CMPXCHG8B instruction support :+
APIC on Chip :-
5) AMD Am5x86 (also AMD Enhanced 486).
Maximum Available of CPUID info entrys:1
Vendor string is : "AuthenticAMD"
Model Info :
Stepping ID is : 4
Model : 15
Family : 4
M field : 0
Compability Flags:
FPU on Chip :+
Virtual Mode Extensions present :-
CPU support I/O breakpoints :-
CPU support 4MB pages :-
Time Stamp Counter Presents :-
CPU have Pentium compatible MSRs :-
P6 Flag: n/a :-
Machine Check Exception Presents :-
CMPXCHG8B instruction support :-
6) Pentium Pro (P6)
Maximum Available of CPUID info entrys:2 <<-------------- !!!!
Vendor string is : "GenuineIntel"
Model Info :
Stepping ID is : 1
Model : 1
Family : 6
M field : 0
Compability Flags:
FPU on Chip :+
Virtual Mode Extensions present :+
CPU support I/O breakpoints :+
CPU support 4MB pages :+
Time Stamp Counter Presents :+
CPU have Pentium compatible MSRs :+
P6 Flag: n/a :+
Machine Check Exception Presents :+
CMPXCHG8B instruction support :+
APIC on Chip :+
Reserved :- ; bit 10
Fast System Call feature :+
Memory Type Range Regs. support :+
Page Global Feature support :+
Machine Check Architecture :+
CMOVxx instructions support :+
IA MMX support :+
7)
Maximum Available of CPUID info entrys:1
Vendor string is : "CyrixInstead"
Compability Flags:
FPU on Chip :+
Virtual Mode Extensions present :-
CPU support I/O breakpoints :+
CPU support 4MB pages :-
Time Stamp Counter Presents :+
CPU have Pentium compatible MSRs :+
P6 Flag: n/a :+
Machine Check Exception Presents :-
CMPXCHG8B instruction support :+
APIC on Chip :-
Reserved :-
Reserved :-
Memory Type Range Regs. support :-
Page Global Feature support :+
Machine Check Architecture :-
CMOVxx instructions support :+
IA MMX support :+
Note: Some Last NexGen Nx586 support CPUID instruction, but never support ID
flag in EFALGS, so check it with #UD hook.
Note: On Cyrix CPUs need to Enable CPUID instruction, setting CPUIDEN bit
in CCR4.
Note: Cyrix Cx6x86 return on CPUID(1) in EAX next data:
YYYYXXMMh - where
YYYY - normally 0s.
XX - value of control register 0FCh
(usually 05h, may be changed to any
other value by user).
MM - Model Unical Revision (according to DIR0)
Note: Cyrix 486s never support CPUID.
Flags Affected: None
CPU mode: RM,PM,VM,SMM
Physical Form: CPUID
COP (Code of Operation): 0FH A2H
Clocks: 486s & Pentium (EAX=1) : 14
486s & Pentium (EAX=0 or EAX>1) : 9
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